FIG. 6 is a partial plan view showing a conventional semiconductor device in which a plurality of semiconductor integrated circuits are formed on a semiconductor wafer. The plurality of semiconductor integrated circuits 1 are arranged on the semiconductor wafer and parting lines 2 are formed between the semiconductor integrated circuits 1. In order to input and output signals between an internal circuit 3 formed in the semiconductor integrated circuit 1 and the outside, testing pads 4 to be used during test and bonding pads 5 to be used after packaging of a product after the test are connected to the internal circuit 3 via wires 6.
On the other hand, testing pads 7 to be used only during test are arranged on the parting line 2 and connected to the internal circuit 3 via wires 8, as shown in FIG. 6. This is because the area of the semiconductor integrated circuit 1 increases as the number of the testing pads 4 formed within the semiconductor integrated circuit 1 increases. When the plurality of semiconductor integrated circuits 1 are cut apart along the parting lines 2 after the test, the testing pads 7 are cut away. Thus, it becomes possible to test the internal circuit 3 without increasing the area of the semiconductor integrated circuit 1.
However, in this case, there is a risk of malfunctioning of the semiconductor integrated circuit 1 because the cutting planes of the wires 8 may be short-circuited with a power supply, a ground power supply or any of the other signal lines when the semiconductor integrated circuits 1 are cut apart along the parting lines 2. For this reason, fuses 9 to be melted off when current flows through them, for example, can be provided in the wires 8 connecting the testing pads 7 to the internal circuit 3, so that even when the wires 8 are short-circuited, the internal circuit 3 can be prevented from being affected by that.
In order to determine the pass/fail of the semiconductor integrated circuit 1 exactly and to reduce the testing time for measuring a large number of test items, it is necessary to provide the multiple testing pads 7 for inputting signals in parallel. Moreover, it is effective to arrange as many testing pads 7 as possible on the parting lines 2 in order to reduce the area of the semiconductor integrated circuit 1.
However, it is difficult to individually and reliably cut off the fuses 9 provided in the wires 8 that are connected to all of the testing pads 7 arranged on the parting lines 2. Furthermore, an additional processing step of cutting off the respective fuses 9 is needed, which increases the testing time.